1. Technical Field
This disclosure is related to calibration of communication links and, more particularly, to skew cancellation in MIPI D-PHY serial links.
2. Discussion of Related Art
In mobile telephone technology, the Mobile Industry Processor Interface (MIPI) D-PHY (physical layer) serial link is the most prevalent and successful high-speed serial link standard used for chip-to-chip communication inside mobile telephones. Conventional MIPI D-PHY links operate at low power and have a relatively short reach, for example, in a printed circuit board (PCB) trace of less than approximately 30 cm. In conventional MIPI D-PHY links, a forward double data rate (DDR) clock scheme is employed for simplified and power-efficient receiver design. The high-speed DDR clock is typically transmitted in quadrature phase relation with the link data. Currently, the typical practical data speed limit is approximately 1.0 Gbs/lane.
In devices that are larger than mobile telephones, such as televisions, LCD displays, tablets/handheld devices, or other devices, a long-reach capability, i.e., longer than 2.0 m, is desirable. At current data speeds, data-clock skew can occur due to mismatch of the twisted pair conductors of clock and data lanes in the MIPI D-PHY serial links and due to CMOS-mismatch-induced phase offset from the transmit (Tx) circuit and the receiver (Rx) front receive end. In long-reach applications, the skew can be large enough to limit the maximum data rate of the link transmission.